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[VHDL-FPGA-Verilog] frame_sync

Description: 帧同步模块的Veriolog源码。 在ModelSim下的一个工程。有测试文件。-frame synchronization module Veriolog source. The ModelSim of a project. A test document.
Platform: | Size: 24576 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] VIDEOGEN_PAL

Description: Spartan-3AN based PAL video sync generator
Platform: | Size: 1024 | Author: t404383 | Hits:

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

Description: This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting -This is usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting
Platform: | Size: 15360 | Author: jeong | Hits:

[VHDL-FPGA-Verilog] vga

Description: vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.-This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.
Platform: | Size: 219136 | Author: jiang nan | Hits:

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